1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, it relates to readout technique in which a current flowing in a memory cell of a semiconductor memory device is detected and its storage state is determined at high speed.
2. Description of the Related Art
There are various kinds of methods of reading out a storage state of a memory cell in a semiconductor memory device. A description will be made with reference to a flash memory which is one of a nonvolatile semiconductor memory device. The flash memory comprises a memory transistor in a memory cell having a floating gate structure, in which information is stored according to an amount of charges (electrons) input to the floating gate of the memory cell. More specifically, in a state where there are many electrons in the floating gate, an inversion layer is not likely to be formed in a channel region, so that a threshold voltage of the memory cell becomes high (defined as a programming state). Meanwhile, in a state where the electrons are discharged from the floating gate, the inversion layer is likely to be formed in the channel region, so that the threshold voltage of the memory cell becomes low (defined as an erasing state). In order to determine whether the state of the selected memory cell is in the programming state or the erasing state at high speed, a reference memory cell having a middle threshold voltage between the programming state and the erasing state is input to a differential input type of sense amplifier circuit.
FIG. 8 shows a basic circuit constitution of a readout circuit in such memory cell (referred to as a conventional example 1 occasionally). The readout circuit shown in FIG. 8 comprises a bias voltage applying circuit 102 in which a predetermined bias voltage is applied to a memory cell 100 selected from memory cells as an object to be read and a reference memory cell 101 to supply a memory cell current flowing in the selected memory cell 100 and the reference memory cell 101 depending on their storage states. The bias voltage applying circuit 102 comprises a load circuit 103, and a bias adjustment circuit 104 which adjusts a bias voltage applied to the selected memory cell 100 and the reference memory cell 101. Therefore, the bias voltage is applied from a predetermined internal power supply voltage to bit lines Bmain and Bref of the selected memory cell 100 and the reference memory cell 101, respectively, through the load circuit 103 and the bias adjustment circuit 104, and reaches the selected memory cell 100 and the reference memory cell 101.
The bias voltage applying circuit 102 converts a memory cell current Imain according to the storage state of the selected memory cell 100 to a voltage level at a first output node Nout1, and converts a reference cell current Iref according to the storage state of the reference memory cell 101 to a voltage level at a second output node Nout2. A voltage difference between both output nodes is detected to determine the storage state of the selected memory cell 100 by a differential amplification type of sense amplifier 105 in a next stage. Therefore, in order to implement high-speed readout, it is necessary to provide a voltage difference across both output nodes sufficiently.
Although the load circuit 103 comprises a transistor in general as shown in the figure, it may be a resistive element instead of the transistor. However, in view of the above circumstances, as shown in the conventional example 1 in FIG. 8, a current-mirror type of load circuit 103 in which a relatively high gain can be provided in a simple structure is used in many cases in general. According to the conventional example 1, it comprises a P-channel MOSFET (referred to as a PMOS hereinafter).
However, as the memory capacity is increased, the number of memory cells to be connected to the bias voltage applying circuit 102 is increased, and electric capacity to be driven by the bias voltage applying circuit 102 tends to be increased. In addition, in view of demands for a readout operation at low voltage, it is necessary to implement the readout operation which is highly tolerant for noise at high speed. As measures for the above issue, it is proposed and implemented that the memory cell array is so constituted that the parasitic capacity of the bit line Bmain of the selected memory cell 100 may be equal to that of the bit line Bref of the reference memory cell 101, and the loads in both current paths are equalized, so that transient response characteristics in the readout operation is equalized.
More specifically, there is a method of speeding up the readout operation, in which the parasitic capacity connected to each input of the sense amplifier is equalized by connecting a bit line of the memory array block adjacent to a memory array block containing the selected memory cell to a bit line of the reference memory cell (for example, refer to JP-A 2003-77282, and D. Elmhurst et. al., “A 1.8V 128 Mb 125 MHz Multi-level Cell Flash Memory with Flexible Read While Write” ISSCC Digest of Technical Papers, pp. 286–287, February, 2003).
In the case of the constitution in which the parasitic capacity is equalized between the bit lines, one of the bit lines is connected to the selected memory cell and the other is connected to the reference memory cell, depending on an address of the selected memory cell (position in the memory array). When the current-mirror type of load circuit shown in FIG. 8 is used as the load circuit of the bias voltage applying circuit, since the constitution is not symmetric, it is designed such that readout performance is prevented from being lowered by the asymmetric characteristics. For example, according to a bias voltage applying circuit disclosed in JP-A 2003-77282 (referred to as the conventional example 2 occasionally hereinafter), as shown in FIG. 9, there is proposed a constitution in which selection transistors 200 are provided to control on/off of the selection transistor depending on an address of the selected memory cell, and the bit line of the selected memory cell is statically connected to one side of the asymmetric load circuit. In addition, according to a bias voltage applying circuit (referred to as the conventional example 3 occasionally hereinafter) disclosed in D. Elmhurst et. al., “A 1.8V 128 Mb 125 MHz Multi-level Cell Flash Memory with Flexible Read While Write” ISSCC Digest of Technical Papers, pp. 286–287, February, 2003, as shown in FIG. 10, there is proposed a constitution in which switch transistors 300 to switch the direction of the current mirror are provided, and one of the switch transistors 300 is turned on according to an address of a selected memory cell to connect a bit line of the selected memory cell to one side of the asymmetric load circuit statically.
However, according to the bias voltage applying circuit of the conventional example 2 shown in FIG. 9, since it is necessary to provide one additional selection transistor 200 to switch the right and left bit lines, an additional resistance component is added to a memory cell current path. As a result, CR (capacity resistance product) of the bit line is increased and the transient characteristics deteriorates, which could hinder the high-speed readout.
Furthermore, according to the bias voltage applying circuit in the conventional example 3 shown in FIG. 10, since the Vds (voltage between a drain and a source) of the PMOS switch transistor 300 becomes almost 0 V, its on resistance is increased and it takes time for a gate potential of the PMOS in the load circuit 103 to reach the same level as that of a drain potential. Therefore, the current mirror operation is not correctly performed for the above period, which could hinder the high-speed readout.
In addition, since the load circuit 103 is asymmetric in the bias voltage applying circuit in either the conventional example 2 or 3, the load capacity at an input node of the next-stage sense amplifier is varied, which could hinder the high-speed readout because of the difference in transient response characteristics.